1. Field of the Invention
This invention relates to semiconductor memory fabrication at the 256 M, 64 M, 16 M and 4 M integration levels.
2. State of the Art
High-density integrated circuitry is principally fabricated from semiconductor wafers. Upon fabrication completion, a wafer contains a plurality of identical discrete die areas which are ultimately cut from the wafer to form individual chips. Die areas or cut dice are tested for operability, with good dice being assembled into separate encapsulating packages which are used in end products or systems.
One type of integrated circuitry comprises memory. The basic unit of semiconductor memory is the memory cell. Capable of storing a single bit of information, the memory cell has steadily shrunk in size to enable more and more cells per area of a semiconductor substrate or wafer. Such enables integrated memory circuitry to be more compact, as well as faster in operation.
Examples of semiconductor memories include ROMs, RAMs, PROMs, EPROMs and EEPROMs. Some emphasize compactness and economy over speed. Others focus on lightning-fast operation. Some store data indefinitely, while others are so temporary they must be refreshed hundreds of time every second. The smallest memory cell comprises the single transistor and single capacitor of a dynamic random access memory (DRAM).
One industry-accepted manner of classifying a memory chip is by the number of final functional and operably addressable memory cells which are contained on a single chip. To maximize density, individual cells are arranged in multiple repeating memory arrays. DRAM fabrication has progressed to the point where millions of functional and operably addressable memory cells can be included in a single chip. Maximizing density of single transistor and other memory cells is a continuing goal in semiconductor memory fabrication.
With each new fabricating generation, the number of memory cells per die has historically increased by a factor of four. For example, what is commonly referred to as the 256 K generation (262,144 addressable DRAM cells per chip) led to the 1 M generation (1,048,576 addressable DRAM cells per chip). The 1 M generation led next to the 4 M generation (4,194,304 addressable DRAM cells per chip). The 4 M generation led to the 16 M generation (16,777,216 addressable DRAM cells per chip), which next led to the 64 M generation (67,108,864 addressable DRAM cells per chip). The industry is presently working on the next factor of four generation, referred to as 256 M (268,435,456 DRAM cells per chip), which has a memory cell pitch of 0.6 micron. Historically, with each generation, the number of addressable memory cells per chip increases exactly by a factor of four with an attendant increase in chip area. However, the increase in chip area has not been directly proportional to the increase in cells due to improved processing techniques which enable the individual memory cell size to be shrunk and thereby to increase in density. Nevertheless, each next generation puts four times the number of memory cells from the previous generation on a single chip.